The present invention relates to a semiconductor memory device (hereafter called RAM) capable of being read and written to, and to a memory test circuit for performing tests on products having such RAM installed.
Conventionally, a memory test circuit has been used to test the RAM of a DRAM, etc. The RAM tests are performed taking into consideration the interrelation between each bit (memory cell) stored in a plurality of memory cells constituting the RAM, and the operation of a decoder built into the memory circuit. Therefore, the RAM tests perform a test on each memory cell by designating memory cells by successively inputting address signals pointing to the memory cells constituting the RAM in a specified sequence. There are many sequential patterns (hereafter called test patterns) for indicating each memory cell address. For example, test patterns known as "CHECKERBOARD," "MARCHING," "GALLOPING," etc.
A conventional memory test circuit for testing a RAM is shown in FIG. 8. This memory circuit 1 is comprised of a memory 10, an internal clock control circuit 12 (hereafter called an internal clock circuit or clock circuit), a first selector 14, a second selector 16 and a third selector 18.
The memory 10 is comprised of a RAM, and has address input terminals 20, a read signal input terminal 22, a write signal input terminal 24 and a data input/output terminal 26. An address signal An is input to the address input terminals 20 by a tester (not shown) exlusively for an external memory test of the memory circuit 1. A read signal is input to the read signal input terminal 22 and a write signal is input to the write signal input terminal 24.
The internal clock control circuit 12 is provided to drive the memory circuit 10 at the time of normal operation. The internal clock control circuit 12 is provided with a test signal input terminal 28, address signal output terminals 30, a read signal output terminal 32, a write signal output terminal 34 and a data terminal 36. The address signal output terminals 30 of the internal clock control circuit 12 are connected to the address input terminals 20 of the memory 10 via the first selector 14. During normal operation, memory cells within the memory 10 are designated by an address signal output from the address signal output terminals 30.
The read signal output terminal 32 of the internal clock control circuit 12 is connected to the read signal input terminal 22 of the memory 10 via the second selector 16. During normal operation, a read signal is output from the read signal output terminal 32.
The write signal output terminal 34 of the internal clock control circuit 12 is connected to the write signal input terminal 24 of the memory 10 via the third selector 18. During normal operation, a write signal is output from the write signal output terminal 34.
The data terminal 36 of the internal clock control circuit 12 is connected to an external data bus 38 and to the data input/output terminal 26 of the memory 10. During normal operation, data output from the data terminal 36 is input from the data input/output terminal 26 to the memory 10 in response to a write signal output from the write signal output terminal 34 (for example, when this write signal goes to a high level). Also during normal operation, data output from the data input/output terminal 26 of the memory 10 is input from the data terminal 36 to the internal clock control circuit 12 in response to a read signal output from the read signal output terminal 32 (for example, when the read signal goes to a high level).
A test signal RAMTEST is input to the test signal input terminal 28 of the internal clock control circuit 12. The potential level of the test signal RAMTEST is a low potential level (hereinafter termed level "0") during normal operation and a high level (hereinafter termed level "1") during testing. During testing, the output of the data terminal 36 of the internal clock control circuit 12 can have one of three states (level "0", level "1" or a high impedance state) and becomes a high impedance state (Hi-Z state) in response to this test signal RAMTEST. As a result, the internal clock control circuit 12 is disconnected from the memory 10 at the time of testing.
The first selector 14 is provided with first input terminals 40, second input terminals 42, a switch terminal 44, and output terminals 46. The first input terminals 40 are connected to the address signal output terminals 30 of the internal clock control circuit 12. An address signal An from outside the memory 10 is input to the second input terminals 42. The test signal RAMTEST from outside the memory circuit 1 is input to the switch terminal 44. The output terminals 46 are connected to the address input terminals 20 of the memory 10.
The first selector 14 outputs an address signal input from the first input terminals 40 to the output terminals 46 at the time of normal operation (when the test signal RAMTEST is at level "0"). At the time of testing (when the test signal RAMTEST is at level "1"), the first selector 14 outputs an address signal An input from the second input terminals 42 to the terminals 46.
The second selector 16 is provided with a first input terminal 50, a second input terminal 52, a switch terminal 54, and an output terminal 56. The first input terminal 50 is connected to the read signal output terminal 32 of the internal clock control circuit 12. A read signal RD from outside the memory 10 is input to the second input terminal 52. The test signal RAMTEST from outside the memory circuit 1 is input to the switch terminal 54. The output terminal 46 is connected to the read signal input terminal 22 of the memory 10.
The second selector 16 outputs a read signal input from the first input terminal 50 to the output terminal 56 at the time of normal operation (when the test signal RAMTEST is at level "0"). On the other hand, at the time of testing (when the test signal RAMTEST is at level "1"), the second selector 16 outputs a read signal RD input from the second input terminal 52 to the output terminal 56.
The third selector 18 is provided with a first input terminal 60, a second input terminal 62, a switch terminal 64, and an output terminal 66. The first input terminal 60 is connected to the write signal output terminal 34 of the internal clock control circuit 12. A write signal WR from outside the memory 10 is input to the second input terminal 62. The test signal RAMTEST from outside the memory circuit 1 is input to the switch terminal 64. The output terminal 66 is connected to the write signal input terminal 24 of the memory 10.
The third selector 18 outputs a write signal input from the first input terminal 60 to the output terminal 66 at the time of normal operation (when the test signal RAMTEST is at level "0"). On the other hand, at the time of testing (when the test signal RAMTEST is at level "1"), the third selector 18 outputs a write signal WR input from the second input terminal 62 to the output terminal 66.
The operation of this memory circuit 1 will now be described below. The description will be given for a case where "GALLOPING" is used as the test pattern. The memory 10 is assumed to be provided with N memory cells (where N is a positive integer). In the case of this description, the number of memory cells N is the same as the number of words (that is the number of words is N).
When testing the memory circuit 1, the test signal RAMTEST is set to level "1." As a result, the data terminal 36 of the internal clock control circuit 12 is put in a high impedance state. Also, the first selector 14 is set so as to output the address signal An input to the second input terminals 42 from the output terminals 46. The second selector 16 is set so as to output a read signal RD input to the second input terminal 52 from the output terminal 56. The third selector 18 is set so as to output a write signal WR input to the second input terminal 62 from the output terminal 66. Accordingly, at the time of testing the memory 10 is driven by signals input from outside the memory circuit 1.
In this state, a "GALLOPING" test is carried out using the following procedure.
(a) First of all, the write signal WR is input from outside the memory 10, N memory cells of the memory 10 are sequentially designated from the address signal An, and level "0" is transferred from the external data bus 38 as data. In this way level "0" is written to all N memory cells of the memory 10. PA1 (b) Next, level "1" is transferred to the external data bus 38 as data. Also, a write signal WR is input from outside the memory circuit 1 and level "1" is written as data to a memory cell among the designated memory cells that is the memory cell under test (the memory cell that is currently being tested). Here, a memory cell with address 0 is the first memory cell to be made the memory cell under test. PA1 (c) Next, in a state where only the cell under test having address 0 from among the memory cells has had level "1" written as data, data stored in certain memory cells is read out. PA1 (d) Next, level "0" is written as data to the memory cell under test having address 0. PA1 (e) Level "1" is then written as data to the memory cell having address 1. As a result, the memory cell having address 1 becomes the cell under test. PA1 (f) Next, when the memory cell with address 1 has been made the cell under test, each memory cell is read according to the test pattern, in a similar operation to that described in (c) above. In this case, reading is carried out by sequentially designating the memory cells in the order of address 1, address 2, address 3, address 1, address 3, address 4, address 1, address 4, address 5, . . . address 1, address N, address 0. PA1 (g) The data stored in the memory cells is read out according to the test pattern using the same operation as described above in (c), until the cell under test becomes the memory cell with address N by sequentially incrementing the memory cell address by one. When the cell under test has address N, reading is carried out up to the memory cell having address N-1, which is one address before the address of the cell under test. PA1 (h) Next, using the operations (a)-(g) described above, the same operation is carried out with a complement pattern of alternate level "1" and level "0" as data. At this time, if the memory 10 is operating normally, level "0" is read as data from the cell under test while level "1" is read as data from memory cells other than the cell under test.
That is, data stored in the memory cell having address 1, which is the subsequent address to the address of the cell under test (address 0), is read out. This read operation is carried out by designating address 1 using address signal An at the same time as inputting a read signal RD. Level "0" is written as data to the memory cell having address 1 using the above described operation (a). Accordingly, if the memory 10 is operating normally, level "0" is read as data from the memory cell having address 1.
Next, data that has been stored in the cell under test having address 0 is read out. The cell under test having address 0 has had level "1" written as data, by the above described operation (b). Accordingly, if the memory 10 is operating normally, level "1" will be read out of the cell under test having address 0 as data.
Next, the data stored in the memory cell having address 1, which is the subsequent address to the cell under test, is read out again. Level "0" has been written as data to the memory cell having address 1, by the above described operation (a), and so if the memory 10 is operating normally, level "0" will be read as data from the memory cell having address 1.
Next, data stored in a memory cell having address 2 subsequent to address 1 is read out. Level "0" has also been written to the memory cell having address 2 using the above described operation (a), and so if the memory 10 is operating normally, level "0" will be read out as data from the memory cell having address 2.
The data stored at the cell under test having address 0 is then read out. Level "1" has been written to the cell under test at address 0 using the above described operation (b), and so if the memory 10 is operating normally, level "1" will be read out from the cell under test having address 0.
Next, the data stored in the memory cell having address 2 is read out again. Level "0" has been written as data to the memory cell having address 2, by the above described operation (a), and so if the memory 10 is operating normally, level "0" will be read as data from the memory cell having address 2.
Next, data stored in a memory cell having address 3 is read out. Level "0" has been written to the memory cell having address 3 using the above described operation (a), and so if the memory 10 is operating normally, level "0" will be read out as data from the memory cell having address 3.
After that, the data stored in each memory cell are read in a similar manner, for address 0, address 3, address 4, address 0, address 4, address 5, and so on, sequentially up to address N. The test pattern for "GALLOPING" is shown in FIG. 9.
In FIG. 9, the numerals represent the memory cell addresses, W represents write and R represents read. Also, the figure on the left hand side of "W" or "R" represents the data value of the written or read. When the cell under test has address 0, after the memory cell having address 1 has been read once, reading is carried out by designating memory cells in the order address 0, address 1, address 2, address 0, address 2, address 3, address 0, address 3, address 4, . . . address 0, address N-1, address N. If the address is considered as a loop, then if the total number of memory cells in the memory 10 is N. a memory cell having address N can be considered to be one cell before the memory cell under test having an address of 0. Further, address N+1 is equivalent to address 0.
The sequence of designating the cell under test is shown in FIG. 10. A memory cell is designated using an X decoder and Y decoder not shown in the memory 10. That is, each memory cell is designated from the input address signal An by designating an X coordinate (the horizontal direction in FIG. 10) using the X decoder and designating a Y coordinate (the vertical direction in FIG. 10) using the Y decoder. In the case of FIG. 10, the output of the X decoder (that is the X coordinate) is changed from a start point to an end point while the output of the Y decoder (the Y coordinate) is fixed, and the output of the Y decoder is then changed sequentially. For each change in the Y decoder, the output of the X decoder is changed from the start point to the end point.
In reading as described above, when level "1" is read as data stored in the cell under test and level "0" is read as data stored in memory cells other than the cell under test, it is confirmed that the memory 10 is operating normally. Conversely, when level "0" is read as data stored in the cell under test and level "1" is read as data stored in memory cells other than the cell under test, it is confirmed that the memory 10 is operating abnormally.
In this way, in the case of a "GALLOPING" test pattern, for one cell under test, reading of three memory cells made up of the cell under test and two consecutive memory cells (for example, memory cells having address 2, address 3) as one set is carried out for every two consecutive memory cells. As a result, if the number of memory cells is N, 3.times.N test patterns are needed for one cell under test. Because all of the N memory cells are sequentially made the cell under test, 3.times.N.sup.2 test patterns become necessary. Also, with a Complement Pattern, since testing is carried out with level "0" and level "1" respectively, written to the cell under test as data, 3.times.N.sup.2 .times.2 test patterns are necessary as a "GALLOPING" test pattern.
Thus in the conventional memory circuit 1, 3.times.N.sup.2 .times.2 test patterns are necessary as a "GALLOPING" test pattern, for example. With any type of test pattern, the test pattern, that is the number of times an address is designated, is proportional to the square of the memory cells. Accordingly, if the memory circuit 1 is made large in scale (the number of memory cells is increased) the number of test patterns increases in proportion to the square of the memory cells, and the number of test patterns becomes enormously large. This means that when storing the address data for this test pattern in memory, if a circuit is prepared to output the address data sequentially depending on the test of the memory circuit 1, there is a problem that the memory capacity for storing the address data becomes enormous.
Further, in order to reduce this memory capacity, a tester for executing the tests becomes necessary, having a computing function for generating the test pattern. This then means that when testing an LSI chip having the memory 10 and the logic circuit on a single chip, an exclusive tester for testing the memory 10 and an exclusive tester for testing the logic circuit are required as a tester exclusively for testing. Therefore, there is a problem that it becomes impossible to carry out testing using a single type of tester when the memory and the logic circuit have been integrated into a single chip.